This application claims the priority of Korean Patent Application No. 2002-43896, filed 25 Jul. 2002 in the Korean Intellectual Property Office (KIPO), which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to an Ethernet network controller, and more particularly, to a network controller and a method of controlling transmitting and receiving buffers of the same.
2. Description of the Related Art
Network controllers commonly include a media access controller (MAC) that functions as an interface between the network controller and a network, and a direct memory access (DMA) controller that functions as an interface between the network controller and a system. In particular, a network controller, such as an Ethernet controller, that adopts a full duplex mode is illustrated in the computer system of FIG. 1. Referring to FIG. 1, the computer system 1000 includes a network controller 100, a memory unit 14, a system bus 18, a plurality of bus masters 16 and 17, and a system bus arbiter 15. The memory unit 14, the system bus arbiter 15, the plurality of bus masters 16 and 17, and the network controller 100 are connected to the system bus 18.
The system bus arbiter 15 arbitrates use of the system bus 18 between a plurality of bus masters 16 and 17 and the network controller 100. The plurality of bus masters 15 and 16 may be interfaced to peripheral devices, such as devices involving the reading and writing data, for example, when driving a sound card or a universal serial bus (USB).
The network controller 100 includes a transmission path for transmitting data and a receiving path for receiving data. A receiving DMA buffer 111 and a receiving MAC buffer 112 and a transmitting DMA buffer 121 and a transmitting MAC buffer 122 are installed in the receiving path and the transmission path, respectively. A single DMA controller provides an interface between each MAC and the system bus 18. In this manner, the transmitting and receiving modules can independently access the system bus 18. For this reason, the computer system 1000 requires an internal arbiter 130 that arbitrates access to the system bus 18.
The internal arbiter 130 receives a request signal Rxreq or Txreq for requesting access to the system bus 18 from the receiving and transmitting modules, transmits this request to the system bus arbiter 15 via the system bus 18, receives a grant GRANT to permit access to the system bus 18 from the system bus arbiter 15, and forwards the grant GRANT to a receiving unit 110 or a transmitting unit 120 via the system bus 18. When the transmitting unit 110 or the receiving unit 120 is permitted access to the system bus 18, data is read from the memory unit 14 and a certain electrical signal is output via the physical layer 140. Otherwise, an electrical signal received via the physical layer 140 is converted and written as data to the memory unit 14.
In this case, the internal arbiter 130 is required to prevent or reduce underflow of the transmitting buffers 121 and 122 or overflow of the receiving buffers 111 and 112, in consideration of the occupancy levels of several buffers, i.e., the transmitting DMA buffer 121, the transmitting MAC buffer 122, the receiving DMA buffer 111, and the receiving MAC buffer 112, which are present at the transmitting and receiving paths of the MAC and DMA, as shown in FIG. 1.
Since data stored in the transmitting DMA buffer 121 is transmitted to the transmitting MAC buffer 122, underflow of the transmitting MAC buffer 122 reduces the performance of the transmitting unit 120. Accordingly, if the transmitting MAC buffer 122 is not empty, underflow of the transmitting DMA buffer 121 does not cause a serious problem during transmission of data. Similarly, since data in the receiving MAC buffer 112 is transmitted to the receiving DMA buffer 111, an overflow, which causes a loss of data, can be easily caused in the receiving DMA buffer 111.
In general, the respective sizes of the internal buffers of a network controller can be set differently according to the application or system of the network controller. If the sizes of the internal buffers are small, the occupancy level of data in each buffer may suddenly change depending on the occupancy of a bus occupied by other masters or a temporal change in the receiving rate of a network may occur.
Also, if the occupancy level of data in a buffer is controlled only in consideration of an absolute occupancy level of a buffer at the transmitting and receiving paths, it is difficult to arbitrate access to data between devices at the transmitting and receiving paths, and thus, overflow or underflow of transmitting and receiving buffers cannot be prevented or reduced.